FPGA SRAM board

set_io v_sync 87
set_io h_sync 88
set_io clk_in 64
set_io reset 66
set_io r0 81
set_io r1 80
set_io r2 79
set_io g0 94
set_io g1 93
set_io g2 91
set_io b0 76
set_io b1 75
set_io b2 74

set_io io0 1
set_io io1 2
set_io io2 3
set_io io3 4
set_io io4 122
set_io io5 121
set_io io6 120
set_io io7 119

set_io a0 138
set_io a1 139
set_io a2 141
set_io a3 142
set_io a4 143
set_io a5 8
set_io a6 9
set_io a7 10
set_io a8 11
set_io a9 12
set_io a10 136
set_io a11 135
set_io a12 134
set_io a13 129
set_io a14 128
set_io a15 117
set_io a16 116
set_io a17 115
set_io a18 114
set_io a19 137
set_io a20 113

set_io cs1 71
set_io we0 7

*********************

Refreshing my verilog learning from HDLbits :

A note on wire vs. reg: The right-hand-side of an assign statement must be a net type (e.g., wire), while the left-hand-side of a procedural assignment (in an always block) must be a variable type (e.g., reg).

                                                                                                  *******

you can do assign w = a; outside of an always block

assign continuously drives a into w

assign out = a&b; makes out equal to a AND’ed with b

it’s a combinational (i.e., memory-less, with no hidden state) function

using assign is the same as using always @(*)

                                                                                            *****

if you don’t declare it, output [3:0] a; will be a vector of type wire

to declare a vector : type [upper:lower] vector_name;

                                                                                              *****

A bitwise operation between two N-bit vectors replicates the operation for each bit of the vector and produces a N-bit output, while a logical operation treats the entire vector as a boolean value (true = non-zero, false = zero) and produces a 1-bit output.

Eg.

output [2:0] out_or_bitwise,
output out_or_logical,

assign out_or_bitwise = a | b;
assign out_or_logical = a || b;

Beware the different symbols for bitwise or logical !
                                                                                                ****

module mod_a ( input in1, input in2, output out );
// Module body
endmodule

When instantiating mod_a inside top_module :

module top_module (
input a,
input b,
output out
);

// Create an instance of “mod_a” named “inst1”, and connect ports by name:
mod_a inst1 (
.in1(a), // Port”in1″connects to wire “a”
.in2(b), // Port “in2” connects to wire “b”
.out(out) // Port “out” connects to wire “out”
// (Note: mod_a’s port “out” is not related to top_module’s wire “out”.
// It is simply coincidence that they have the same name)
);

                                                                                                ***

ALWAYS BLOCKS :

Clocked: always @(posedge clk)

Procedural blocks have a richer set of statements (e.g., if-then, case), cannot contain continuous assignments,

Clocked always blocks create a blob of combinational logic just like combinational always blocks, but also creates a set of flip-flops (or “registers”) at the output of the blob of combinational logic. Instead of the outputs of the blob of logic being visible immediately, the outputs are visible only immediately after the next (posedge clk).

In a locked always block, only use procedural non-blocking assignment: (x <= y;)

                                                                                            ***

Combinational circuits must have a value assigned to all outputs under all conditions. This usually means you always need else clauses or a default value assigned to the outputs.

This can cause the Warning (10240): … inferring latch(es) error message

                                                                                            ***

Saw some inspiring machines in Munich :

Barrels would be cool to incorporate into my next prototype.

I wonder if I could make an analog feedback set up with linear actuators, a screen and camera…

I love the scientific instrument aspect. The monitor hovering on the side could be cool to incorporate.

 

*****

Check out this analog video feedback setup… could I do a miniature version ? :

 

****

One reaction to the museum visit it to think of what makes something look like a machine.

• an agglomeration of mainly metal (especially machined aluminum and folded steel) and plastic modules
• rotation and linear motion, symmetry about a central axis or a pile of modules facing the user

If I wanted to focus on the technical object itself, I could work on a custom cooling setup, with thin curving pipes, knobs that allow for various kinds of custom fine control, screens and cameras on various linear axes for feedback loop control.

A DIY water cooler :

A custom keyboard from https://keyboards.tanebox.com/a/blog/939/ :

I like the exposed keyboard that extends into a circuit board with chips on the top. Could it be possible to make a kind of reprogrammable FPGA video synth computer ? Perhaps I could also learn things about video by taking a video file from a an SD card and then moving it into a dual port DRAM memory to be displayed.

This gets at something that feels important : I am always trying to get myself to some harder to get to place, with the help of DIY tech, before making artsy stuff. It’s almost like I feel I’m not competitive enough starting from the most accessible starting point (classical art like drawing, painting, sculpture). Sam suggested that I combine my interest in hardware with software. Can I make a kind of custom programmable computer that is my own and then program it in a low level language (like assembly or verilog)?

I love the windy wire plug found on the mechanical keyboard subreddit :

From https://spectrum.ieee.org/yugoslavia-diy-microcomputer :

Keyboard buttons from Mouser : https://www.mouser.fr/ProductDetail/E-Switch/KS1100OA1AF060?qs=gt1LBUVyoHkJwqhwHM2wRw%3D%3D

***

Or, in the totally opposite direction (not going for gimmicks or flashiness), super inexpensive DRAM chips (1 euro for 16Mbit) :

https://www.mouser.fr/ProductDetail/ISSI/IS42S16100H-7TL?qs=yfIbTn1BQ2BEUPfKEYbGCA%3D%3D

****

Had a thought : I am basically trying to “play” the VGA format itself like an instrument.

****

So making a pin that is both input and output for an FPGA is not so simple ! This post helped : https://electronics.stackexchange.com/questions/33144/birectional-i-o-pin-in-verilog

My attempts to make diagrams :

 

I also cleaned up the code a bit, making vectors with indices and following naming conventions :

I can see evidence of something being recorded and played back out of sync (only when rpi input provides H&V and the FPGA used the rpi 41MHz pixel clock or the 100MHz clock) but it’s far from working completely.

I can send external clocks that are divisions of 41MHz clock (20.5MHz, 10.25MHz) when rpi is supplying the H&V and it just barely works.

The FPGA works with external 25MHz clock also, but I can’t see any recordings.

*EDIT* I can get pretty clear recordings with the RPI clock and H&V after fiddling. Still no luck with recording RPI color information and then showing it at FPGA H&V with either pixel clock. I have gotten rid of the test colors and now am showing full screen FPGA. Twiddled 4 versus 3 bits on the output.

`default_nettype none

module vga_sync_test(

input wire clk_in,
input wire reset,

input wire rec, // Direction of io, 1 = set output, 0 = read input

//RASPBERRY PI
input wire [3:0] r_in,
input wire [3:0] b_in,
input wire [3:0] g_in,

//VGA OUT
output reg [3:0] r_out,
output reg [3:0] b_out,
output reg [3:0] g_out,

output wire h_sync,
output wire v_sync,

//SRAM

output reg [20:0] addr,
inout wire [7:0] io, // inout must be type wire

output wire cs_1,
output reg we_0

);

wire [7:0] data_in;
wire [7:0] data_out;

reg [7:0] a, b;

assign io = rec ? a : 8'bzzzzzzzz;

assign data_out = b;

assign data_in[1:0] = r_in[3:2];
assign data_in[3:2] = b_in[3:2];
assign data_in[5:4] = g_in[3:2];
assign data_in[7:6] = 2'b00;

wire display_en;
wire [11:0] h_count;
wire [11:0] v_count;

assign cs_1 = 0; // low to select, high to deselect

localparam h_pixel_max = 1280;
localparam v_pixel_max = 960;
localparam h_pixel_half = 640;
localparam v_pixel_half = 480;


//SRAM address counter

always @(posedge clk_in) begin
    if (reset)
        addr <= 0;
    else
        addr <= addr+1;
    end


//REC control

always @(posedge clk_in) begin
      b <= io;
      a <= data_in;
     if (rec) begin
          we_0 <= addr[0]; //not sure why it isn't the inverse of addr[0] but that doesn't make the inverse on 'scope
     end
     else begin
          we_0 <= 1;
     end
end

//VGA COLOR OUT

always @(posedge clk_in) begin
if (display_en) begin
if (h_count < h_pixel_half
&& v_count < v_pixel_half) begin

r_out[1:0] <= data_out[1:0];
r_out[2] <= 1'b0;
g_out[1:0] <= data_out[3:2];
g_out[2] <= 1'b0;
b_out[1:0] <= data_out[5:4];
b_out[2] <= 1'b0;

end else if (h_count > h_pixel_half
&& v_count < v_pixel_half) begin


r_out <= 3'b000;
g_out <= 3'b111;
b_out <= 3'b000;

end else if (h_count < h_pixel_half
&& v_count > v_pixel_half) begin


r_out <= 3'b111;
g_out <= 3'b000;
b_out <= 3'b000;

end else begin


r_out <= 3'b111;
g_out <= 3'b111;
b_out <= 3'b111;

end
end else begin

r_out <= 3'b000;
g_out <= 3'b000;
b_out <= 3'b000;
end
end

vga_sync vga_s(
.clk_in(clk_in),
.reset(reset),
.h_sync(h_sync),
.v_sync(v_sync),
.h_count(h_count),
.v_count(v_count),
.display_en(display_en) // '1' => pixel region
);

endmodule

 

Here is the complete pcf :

set_io v_sync 87
set_io h_sync 88
set_io clk_in 64
set_io reset 66

set_io io[0] 1
set_io io[1] 2
set_io io[2] 3
set_io io[3] 4
set_io io[4] 122
set_io io[5] 121
set_io io[6] 120
set_io io[7] 119

set_io io[8] 45
set_io io[9] 47
set_io io[10] 48
set_io io[11] 49
set_io io[12] 28
set_io io[13] 26
set_io io[14] 25
set_io io[15] 24

set_io addr[0] 138
set_io addr[1] 139
set_io addr[2] 141
set_io addr[3] 142
set_io addr[4] 143
set_io addr[5] 8
set_io addr[6] 9
set_io addr[7] 10
set_io addr[8] 11
set_io addr[9] 12
set_io addr[10] 136
set_io addr[11] 135
set_io addr[12] 134
set_io addr[13] 129
set_io addr[14] 128
set_io addr[15] 117
set_io addr[16] 116
set_io addr[17] 115
set_io addr[18] 114
set_io addr[19] 137
set_io addr[20] 113

set_io addr[21] 38
set_io addr[22] 39
set_io addr[23] 41
set_io addr[24] 42
set_io addr[25] 43
set_io addr[26] 52
set_io addr[27] 56
set_io addr[28] 58
set_io addr[29] 60
set_io addr[30] 61
set_io addr[31] 34
set_io addr[32] 33
set_io addr[33] 32
set_io addr[34] 31
set_io addr[35] 29
set_io addr[36] 23
set_io addr[37] 22
set_io addr[38] 21
set_io addr[39] 20
set_io addr[40] 37
set_io addr[41] 19

set_io cs_0 144
set_io cs_1 71
set_io cs_2 44
set_io cs_3 63

set_io we_0 7
set_io we_1 50

set_io rec 62

set_io r_in[0] 107
set_io r_in[1] 106
set_io r_in[2] 105
set_io r_in[3] 104
set_io g_in[0] 97
set_io g_in[1] 96
set_io g_in[2] 95
set_io g_in[3] 112
set_io b_in[0] 102
set_io b_in[1] 101
set_io b_in[2] 99
set_io b_in[3] 98

set_io r_out[0] 81
set_io r_out[1] 80
set_io r_out[2] 79
set_io r_out[3] 78
set_io g_out[0] 94
set_io g_out[1] 93
set_io g_out[2] 91
set_io g_out[3] 90
set_io b_out[0] 76
set_io b_out[1] 75
set_io b_out[2] 74
set_io b_out[3] 73

****

Added the third SRAM and having issues, commented out one new pin at a time and it seems like address 18 (on pin 20) is problematic. When I remove this pin everything else functions well enough for a memory with a missing pin however.

`default_nettype none

module vga_sync_test(

input wire clk_in,
input wire reset,

input wire rec, // Direction of io, 1 = set output, 0 = read input

//RASPBERRY PI
input wire [3:0] r_in,
input wire [3:0] b_in,
input wire [3:0] g_in,

//VGA OUT
output reg [3:0] r_out,
output reg [3:0] b_out,
output reg [3:0] g_out,

output wire h_sync,
output wire v_sync,

//SRAM

output reg [20:0] addr,
inout wire [7:0] io, // inout must be type wire

output wire cs_1,
output wire cs_0,
output reg we_0

);

wire [7:0] data_in;
wire [7:0] data_out;

reg toggle;

reg [7:0] a, b;

assign io = rec ? a : 8'bzzzzzzzz;

assign data_out = b;

assign data_in[1:0] = r_in[3:2];
assign data_in[3:2] = b_in[3:2];
assign data_in[5:4] = g_in[3:2];
assign data_in[7:6] = 2'b00;

wire display_en;
wire [11:0] h_count;
wire [11:0] v_count;

localparam h_pixel_max = 1280;
localparam v_pixel_max = 960;
localparam h_pixel_half = 640;
localparam v_pixel_half = 480;

// CS: low to select, high to deselect

assign cs_0 = toggle ? 1 : 0;
assign cs_1 = toggle ? 0 : 1;

//SRAM address counter

always @(posedge clk_in) begin

if (addr == 0) begin
toggle <= toggle+1;
end

if (reset) begin
addr <= 0;
end else begin
addr <= addr+1;

end
end


//REC control

always @(posedge clk_in) begin

b <= io;
a <= data_in;

if (rec) begin
we_0 <= addr[0]; //not sure why it isn't the inverse of addr[0] but that doesn't make the inverse on 'scope
end
else begin
we_0 <= 1;
end
end

//VGA COLOR OUT

always @(posedge clk_in) begin
if (display_en) begin

r_out[3:2] <= data_out[1:0];
r_out[1:0] <= data_out[1:0];
g_out[3:2] <= data_out[3:2];
g_out[1:0] <= data_out[3:2];
b_out[3:2] <= data_out[5:4];
b_out[1:0] <= data_out[5:4];

end else begin

r_out <= 4'b0000;
g_out <= 4'b0000;
b_out <= 4'b0000;
end
end

vga_sync vga_s(
.clk_in(clk_in),
.reset(reset),
.h_sync(h_sync),
.v_sync(v_sync),
.h_count(h_count),
.v_count(v_count),
.display_en(display_en) // '1' => pixel region
);

endmodule

***

I made an animated video of the assembly of the board :

When I make the next board I’ll  record the eagle CAD and make another video.